Resulting Challenges

The economic realities of building, maintaining and operating today’s typical state-of-the-art facility have resulted in numerous challenges and limitations.

Design Flexibility:
Most products incorporating semiconductor devices have a very short life cycle and changes in the semiconductor market occur rapidly. This situation demands high degrees of flexibility and innovation to constantly adjust to the rapid pace of change.

However, with today’s economic pressures, companies face high risks when placing ‘novel’ designs into large volume production lines and the costs of failure can decimate a company. Under the circumstances, it is difficult, if not impossible, for designers to test and implement radical changes.

Designers today face challenges unseen by their early predecessors, like:

• Research and Development is often accomplished in shared facilities thousands of miles away from the designers
• Prototyping is restricted to standardized flows
• A disrupted design process causes frustration and less creative solutions
• Small volume experimentation is virtually impossible
• Design innovation is discouraged due to the high cost/risk levels
• Young engineers are not able to be trained in realistic fabrication settings

Shared Resources:
Due to the obvious economic pressures, fabs usually ‘share’ facilities amongst several competitive companies to perform research and development. Challenges arising from such a scenario include:

• Geometrically increased security issues and access restrictions
• Generic design of equipment to allow for the widest possible application to shared partner applications
• Participating companies forced to conform designs and technologies to fit generic manufacturing requirements
• Innovation is repressed

Research and Development and Early Product Ramp up Cycle Times:
By its very nature, Research and Development is small volume activity. Due to the inhibitions of the current cost structure on all activity of small volume every step of the R&D chain is set with significant increases in the times to perform the steps

• New materials have to be developed to scale up to large wafer sizes before testing or utilization… a hurdle which may become so large at 18 inch sizes that some new materials may never make it
• New equipment concepts, designs and improvements must be proven on the largest wafer dimension before any sales can be realized to support the innovation.
• The number of players capable of providing equipment solutions is minimal due to the cost
• Tooling improvements take longer in some cases (like EUV) perhaps causing the entire industry to backlog its innovation cycle time
• Affordable new design development on “MPW” vehicles run at limited schedules on standard processing – the concept of a continuous flow of new design options/enhancements/reliability improvements is long gone.
• The costliness of the cleanroom environment puts a premium on space in the cleanroom… tools like test and packaging tools which need less stringent requirements must be segregated for economic logic.
• New devices or non-standard processes have extreme hurdles to overcome to be developed even in the few shared/old tool facilities existing for the purpose.

NEXT

Companies face high risks when placing ‘novel’ designs into large volume production lines and the costs of failure can decimate a company.